Appendix A
16
(50)Write all the CMOS values currently in the BIOS stack areas back into the
CMOS. Write CMOS; Write all CMOS values back to RAM and clear screen.
(50)Check for dual freq in CMOS.
(50)Display CPU type and speed.(Beep)=2
test.[Beep]=none Custom chip set or custom platform.
(51)Memory size display adjusted due to relocation/shadow. Memory test above 1M
1 base register test about to start.
boot enable; Enable parity checker; Enable NMI, Enable cache before boot.
(51)Check CMOS VDU configuration.
(52)Memory testing/initialization below 1M complete. Going to save memory size
information. Going to prepare to go back to real mode. DMA unit-
(52)Initialize all ISA ROMs. Later PC
I initializations(PCI BIOS only).PnP
initializations(PnP BIOS only).Program shadow RAM according to setup settings.
Program parity according to setup setting. Power Management initialization.
Initialize option ROMs; initialize any option ROMs present from
(52)DMA controller initialize.
(52)Test keyboard.(Beep)=2
3.(52)Perform LAR instruction test.
(53)Memory size information is saved. CPU registers are saved. G
(53)If it is not a PnP BIOS, initialize serial & parallel ports. Initialize time value in
BIOS data area. Initialize time value; Initialize time value in 40h BIOS data area.
(53)Initialize interrupt controller.
(54)Shutdown successful, CPU in real mode. Going to re
during preparation for shutdown. About to check F/F latch
(54)Initialize primary display adapter.
(54)Set key click if enabled.(Beep)=2
1.(54)Perform VERR instruction test.
(55)Registers restored. Going to d
isable gate A20 address line. F/F latch for both
(55)Initialize secondary display adapter.
(55)EMS configuration Setup.
disable successful. BIOS ROM data area about to be checked.
DMA unit 1 and 2 programming over and about to initialize 8259 interrupt
(56)No display adapters installed.
(57)A20 address line disable successful. BIOS ROM data area check halfway. BIOS
ROM data area check to be com
plete.8259 initialization over.
(57)Init primary VDU mode.
(58)Memory size adjusted for relocation/shadow. Going to clear Hit<DEL>
message. BIOS ROM data area check over. Going to clear Hit<ESC> message.8259
(58)Memory interleave configure.
(58)Test for unexpected interrupts.(Beep)=2
.(58) Perform A20 gate test.
(59)Hit<ESC> message cleared.<Wait..> message displayed. About to start DMA
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