
Appendix A
19
(72)Keyboard interface test over, mouse interface test started.
(72)High order address test.
figuration errors.(Beep)=2
3.(72) Real time clock test.
(73)Global data initialization for keyboard/mouse over.
(74)About to test serial port.
(74)Display ’SETUP’ prompt
and about to start floppy setup.
(74)Parity error on bus after memory test, system halted.
(75)Start of protected mode test.
(76)Hard disk setup about to start.
(76)Prepare to enter protected mode.
(76)Check for keyboard errors. (Beep)=2
3.Initialize hardware interrupt
(77)Hard disk setup over.
(77)Test software exceptions.
(78)Prepare to return to real mode.
(78)Detect and test CoProcessor.
(79)About to initialize timer data area.
(7A)Timer data initialized and about to verify CMOS battery power.
(7A)Determine/Init COM channels.
(7B)CMOS battery verification over.
(7C)High order address test failure.
(7C)Set up hardware interrupts vectors.(Beep)=2
1.Determine LPT channels.
(7D)About to analyze POST results. About t
o analyze diagnostic test results for
(7D)Enter cache controller test.
(7E)CMOS memory size updated.
(7E)Exit cache controller test.
(7E)Test CoProcessor if present.(Beep)=2
(7F)Look for <DEL>key and get into CMOS setup if found About to check
(7F)Copy System ROM to high RAM.
(80)Determine math CoProcessor is present.
rted, clearing output buffer, checking for stuck key, About to
issue keyboard reset command. About to give control to optional ROM in segment
(80)Disable onboard Super I/O ports and IRQs.(Beep)=3
(81)Keyboard reset error/stuck key found. About to issue keyboard controller
interface test command. Optional ROM control over.
(81)late POST device initialization.
(82)Keyboard controller interface test over. About to write command byte and Init
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